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REAL Developer SOLUTIONS
for Multicore and
Multiprocessing Designs

2010 Multicore Expo

ME721: Maximizing Multichannel DRAM Performance by Invisible Load Balancing
ADVANCED LEVEL SESSION
Day	04/28/10
Time	15:00-15:45
Company	Sonics, Inc.
Abstract	Complex SoCs with massive appetites for memory bandwidth are now common. They can have 100 or more cores, each demanding carefully tuned access to higher bandwidth DRAMs. Burst sizes in DDR3 systems have doubled, introducing an efficiency penalty that can result in a loss of performance for the system. Increasingly, designers are deciding to employ multi-channel memory solutions and newer memory technologies to maintain efficiency while increasing overall memory bandwidth. Load balancing approaches are key to achieving the required performance with multichannel memories. This presentation will detail the techniques used to deploy multichannel DRAMs and make recommendations for optimal tuning of multichannel memory system performance.
Speaker	Drew Wingard CTO, Sonics, Inc. Dr. Drew Wingard co-founded Sonics in September 1996 and has been chief technical officer and secretary since March 1997. Prior to co-founding Sonics, Wingard led the development of advanced circuit and CAD methodology for MicroUnity Systems Engineering, Inc. from 1994 to 1996. He also co-founded and worked at Pomegranate Technology from 1992 to 1994, where he designed an advanced SIMD multimedia processor. Since December 2001, Wingard has served as secretary and a director of the OCP-IP, a non-profit trade organization. He received a B.S. from the University of Texas, Austin and an M.S. and a Ph.D. from Stanford University, all in electrical engineering.